• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a method of forming a MOS transistor, and in particular, the method includes forming a gate insulating film and a gate electrode on a semiconductor substrate, forming a first spacer on a sidewall of the gate electrode, and a gate except for the first spacer. Forming a buffer insulating film thicker than the gate insulating film on the upper surface of the electrode and the substrate surface exposed by the gate electrode, removing the first spacer, forming a second spacer on the sidewall of the gate electrode, and then forming a source / drain region. And removing the buffer insulating film corresponding to the upper portion of the substrate to be formed, and forming a source / drain region in the substrate near the etched buffer insulating film edge by injecting the substrate and other conductive impurities at a high concentration. Therefore, according to the present invention, the buffer insulating film is formed on the upper surface of the gate electrode except for the gate electrode sidewall and the spacer and the lower portion of the spacer, thereby minimizing the hot-carrier effect occurring near the gate electrode edge. It is possible to improve the driving capability of the transistor by compensating for the deterioration of the gate prince field condition caused by the insulating film, thereby implementing a highly reliable semiconductor device.
    公开号:KR20000027815A
    申请号:KR1019980045846
    申请日:1998-10-29
    公开日:2000-05-15
    发明作者:김광수；강영석
    申请人:김영환；현대전자산업 주식회사；
    IPC主号:
    专利说明:

    How to Form Morse Transistor
    BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device having a MOS transistor, and more particularly, to a gate fringe field while preventing a hot-carrier effect with a spacer structure consisting of a silicon oxide film and a silicon nitride film on the gate electrode sidewalls and edges. Field of the Invention The present invention relates to a method of forming a MOS transistor capable of compensating performance due to reduction.
    In general, the MOS transistor, which is a semiconductor device, is formed of an insulating material on both sidewalls of the gate electrode of the transistor to prevent the transistor from deteriorating the electrical characteristics of the transistor when the electric field is strongly formed at the drain edge part. Form a spacer. This spacer adjusts the impurity concentration in the substrate near the gate electrode edge to be lower than the source / drain region, thereby lowering the electric field at the drain edge portion.
    Previously, many silicon oxide films (SiO 2 ) were used as the film quality of the spacer. When TiSi x is used as the silicide material to be used in the subsequent process, Ti reacts with SiO 2 , causing short- circuit between the gate and the source / drain. Recently, a silicon nitride film (SiNx) that does not react with silicon (Si) and titanium (Ti) is used as a film quality of a spacer. However, even in this case, since a defect caused by interlayer stress is generated at the subsequent heat treatment on the surface where the silicon nitride film and the substrate are in contact with each other, a thin film buffer insulating layer capable of alleviating the stress between the spacer and the substrate is required.
    1A to 1D are process flow charts sequentially illustrating a process of forming a MOS transistor according to the prior art, which forms an element isolation film (not shown) on a silicon substrate 10 as a semiconductor substrate, as shown in FIG. 1A. After the gate insulating film 12 and the gate electrode 14 which are sequentially stacked on the substrate surface between the device isolation layers are formed, impurities of conductive conductivity different from that of the substrate are injected to the substrate surface near the edge of the gate electrode 14 at low concentrations so that LDD ( Lightly Doped Drain) region 16 is formed.
    Subsequently, as shown in FIG. 1B, an insulating film 18 for the buffer is formed on the upper surface of the gate electrode 14 and the entire surface of the substrate exposed by the gate electrode.
    1C to 1D, the silicon nitride film 20 is deposited on the entire buffer insulating film 18, and the silicon nitride film 20 is etched by a dry etching process to form spacers on both sidewalls of the gate electrode 14. 20 '). At this time, the buffer insulating film 18 on the upper surface of the gate electrode 14 and the substrate surface is selectively removed so that only the buffer insulating film 18 'between the gate electrode 14 and the spacer 20' remains. Subsequently, a high concentration of impurity ions are implanted to form the source / drain regions 22 under the substrate near the edge of the spacer 20 '.
    The buffer insulating film 18 ′ of the transistor having the above manufacturing process sequence is formed to have the same thickness as the sidewall of the gate electrode 14 or the top surface of the LDD region 16. Accordingly, the thicker the thickness of the buffer insulating film 18 ′ corresponding to the upper portion of the LDD region 16 is, the better the hot-carrier effect is. On the other hand, the buffer insulating film 18 'corresponding to the sidewall of the gate electrode 14 is less related to the hot-carrier effect and rather to the driving capability of the transistor. Therefore, as the thickness of the buffer insulating film 18 'on the sidewall of the gate electrode 14 becomes thicker, the performance due to the decrease of the gate prince field is gradually decreased. There is a problem that it is difficult to secure a MOS transistor having a buffer insulating film that satisfies all the field conditions.
    The object of the present invention is to minimize the thickness of the insulating film for the buffer between the gate electrode sidewall and the spacer, while increasing the thickness of the insulating film for the buffer between the spacer and the substrate to increase the thickness of the hot-carrier to minimize the problem of the prior art as described above. The present invention provides a method of forming a highly reliable MOS transistor suitable for both effect and gate prince field conditions.
    1A to 1D are process flowcharts sequentially illustrating a process of forming a MOS transistor according to the prior art;
    2A to 2F are process flowcharts sequentially illustrating a process of forming a MOS transistor according to the present invention.
    * Description of the symbols for the main parts of the drawings *
    100 silicon substrate 102 gate insulating film
    104: gate electrode 106: LDD region
    108: first spacer 110,110 ': insulating film for buffer
    112 ': Second spacer 114: Source / drain region
    In order to achieve the above object, the present invention provides a MOS transistor having a gate electrode and a source / drain region formed on a semiconductor substrate, the method comprising: forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a first spacer on the sidewall of the gate electrode; Forming a buffer insulating film thicker than the gate insulating film on the top surface of the gate electrode except for the first spacer and the substrate surface exposed by the gate electrode; removing the first spacer; Removing the buffer insulating film corresponding to the upper part of the substrate on which the second spacer is to be formed and then forming the source / drain region; and injecting the substrate and other conductive impurities at a high concentration into the source / substrate near the edge of the buffer insulating film etched. Forming a drain region, All.
    In the method for forming the MOS transistor of the present invention, it is preferable that the first spacer has a thickness thinner than that of the second spacer. After forming the gate electrode, the method further includes forming a LDD region in the substrate near the edge of the gate electrode by implanting the substrate and other conductive impurities at low concentration. The first spacer and the second spacer are preferably formed of a silicon nitride film, and the buffer insulating film is preferably formed of a silicon oxide film.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    2A to 2F are process flowcharts sequentially illustrating a process of forming a MOS transistor according to the present invention. For reference, in this embodiment, an n-channel MOS transistor is used.
    First, an element isolation film (not shown) defining an active region of an element is formed in the p-type silicon substrate 100 as a semiconductor substrate. As shown in FIG. 2A, the gate insulating layer 102 and the gate electrode 104 are formed on the surface of the active region of the substrate 100. Next, n-type impurities, which are conductive impurities different from the substrate, are implanted at low concentration to form the LDD region 16 into which the n-type impurities are implanted on the surface of the substrate near the edge of the gate electrode 14. Then, a thin silicon nitride film 108 is deposited on the upper surface of the gate electrode 14 and the entire surface of the substrate exposed by the gate electrode 14.
    Subsequently, as shown in FIG. 2B, the silicon nitride film 108 is etched by a dry etching process to form first spacers 108 ′ on both sidewalls of the gate electrode 104.
    As shown in FIG. 2C, the resultant is subjected to an oxidation process, and is thicker than the gate insulating layer 102 on the top surface of the gate electrode 104 except for the first spacer 108 ′ and the substrate surface exposed by the gate electrode 104. The buffer insulating film 110 is formed.
    Then, as shown in FIG. 2D, only the first spacer 108 ′ is selectively removed using a phosphate dip process.
    Subsequently, as shown in FIG. 2E, the silicon nitride layer 112 is deposited thicker than the first silicon nitride layer 108 deposited on the entire surface of the resultant, and the silicon nitride layer 112 is etched by a dry etching process to gate as shown in FIG. 2F. The second spacer 112 ′ is formed on both side walls of the electrode 104. Thereafter, the buffer insulating layer corresponding to the upper portion of the substrate on which the source / drain regions are to be removed is removed so that only the buffer insulating layer 110 ′ corresponding to the upper surface of the gate electrode 104 and the lower portion of the second spacer 112 ′ remains. The source / drain region 114 is formed in the substrate 100 near the edge of the buffer insulating layer 110 ′ under the second spacer 112 ′ by ion implantation of a conductive n-type impurity different from the substrate.
    Subsequently, although not shown in the drawings, the silicide process, the interlayer insulating film process, and the wiring process are sequentially performed to complete the MOS transistor of the present invention.
    By the manufacturing process, the present invention ensures the buffer insulating films 110 and 110 'made of a silicon oxide film thicker than the gate insulating film only on the upper surface of the gate electrode 104 and the spacer 112' except the sidewalls of the gate electrode 104.
    As described above, according to the present invention, the buffer insulating film is formed on the upper surface of the gate electrode except for the space between the gate electrode sidewall and the spacer and the lower portion of the spacer, thereby minimizing the hot-carrier effect occurring near the edge of the gate electrode. By compensating for the deterioration of the gate prince field condition caused by the insulating film for the buffer, it is possible to improve the driving capability of the transistor, thereby implementing a highly reliable semiconductor device.
    On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] In a MOS transistor having a gate electrode and a source / drain region formed on a semiconductor substrate,
    Forming a gate insulating film and a gate electrode on the semiconductor substrate;
    Forming a first spacer on sidewalls of the gate electrode;
    Forming a buffer insulating film thicker than a gate insulating film on an upper surface of the gate electrode except for the first spacer and a substrate surface exposed by the gate electrode;
    Removing the first spacer;
    Forming a second spacer on the sidewall of the gate electrode, and removing a buffer insulating layer corresponding to an upper portion of a substrate on which a source / drain region is to be formed; And
    And forming a source / drain region in the substrate near the etched buffer insulating film edge by implanting a substrate and other conductive impurities in a high concentration.
    [2" claim-type="Currently amended] The method of claim 1, wherein the first spacer has a thickness thinner than that of the second spacer.
    [3" claim-type="Currently amended] The method of claim 1, further comprising forming a LDD region in the substrate near the edge of the gate electrode by injecting the substrate and other conductive impurities at a low concentration after forming the gate electrode. .
    [4" claim-type="Currently amended] The method of claim 1, wherein the first spacer and the second spacer are formed of a silicon nitride film.
    [5" claim-type="Currently amended] The method of claim 1, wherein the buffer insulating film is formed of a silicon oxide film.
    类似技术:
    公开号 | 公开日 | 专利标题
    US6512258B2|2003-01-28|Semiconductor device and method of manufacturing same
    US8106456B2|2012-01-31|SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics
    US7282415B2|2007-10-16|Method for making a semiconductor device with strain enhancement
    US7535067B2|2009-05-19|Transistor in semiconductor devices and method of fabricating the same
    KR100237279B1|2000-01-15|Misfet, complementary misfet and manufacturing method thereof
    US7399679B2|2008-07-15|Narrow width effect improvement with photoresist plug process and STI corner ion implantation
    JP4361886B2|2009-11-11|Semiconductor integrated circuit device and manufacturing method thereof
    KR100212693B1|1999-08-02|Si/sige mos fet transistor and its fabrication process
    US6693013B2|2004-02-17|Semiconductor transistor using L-shaped spacer and method of fabricating the same
    DE10255849B4|2006-06-14|Improved drain / source extension structure of a field effect transistor with high permittivity doped sidewall spacers and method of making the same
    KR100234700B1|1999-12-15|Manufacturing method of semiconductor device
    JP4148717B2|2008-09-10|Manufacturing method of semiconductor device
    KR100214468B1|1999-08-02|Method for fabricating cmos
    US7683405B2|2010-03-23|MOS transistors having recesses with elevated source/drain regions
    KR100526366B1|2005-11-08|Semiconductor device and method for manufacturing the same
    KR970002266B1|1997-02-27|Semiconductor devices and integrated circuits using sidewall spacer technology
    US6838733B2|2005-01-04|Semiconductor device and fabrication method with etch stop film below active layer
    KR100794094B1|2008-01-10|Method of manufacturing a transistor in a semiconductor device
    KR100639679B1|2006-10-30|method of fabricating transistor including buried insulating layer and transistor fabricated thereby
    KR20000030013A|2000-05-25|Integrated circuit with differing gate oxide thickness and process for making same
    US7226872B2|2007-06-05|Lightly doped drain MOS transistor
    EP0495650B1|1996-12-04|Method of fabricating field-effect transistor
    US6399451B1|2002-06-04|Semiconductor device having gate spacer containing conductive layer and manufacturing method therefor
    JP4093855B2|2008-06-04|Manufacturing method of semiconductor device
    US6180988B1|2001-01-30|Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure
    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-10-29|Application filed by 김영환, 현대전자산업 주식회사
    1998-10-29|Priority to KR1019980045846A
    2000-05-15|Publication of KR20000027815A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980045846A|KR20000027815A|1998-10-29|1998-10-29|Method for fabricating mos fet|
    [返回顶部]